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page 1 april 2003 FS8308 low power pll fr equency synthesizer ic advance information princeton technology corp. reserves the ri ght to change the product described in this datasheet. all information con- tained in this datasheet is subject to change without prior notice. princeton technology corp. assumes no responsibility for the use of any circuits shown in this datasheet. description the FS8308 is a serial data i nput, phase-locked loop ic with programmable input and ref- erence frequency dividers. when combined wi th a vco, this ic becomes the core of a very low power frequency synthesizer well-s uited for mobile communication applications, e.x. paging systems and family radio service (frs). there are some features implemented in this ic, including an 18-bit programmable i nput frequency divider, a terminal for refer- ence oscillator buffer output, as well as st and-by control through programming, and etc. details are listed in the following. features ? up to 40 mhz external crys tal oscillator reference fr equency under normal condition ? low current consumption (i dd,total typically 1.2 ma at f fin = 500 mhz and v dd1 = 1.0 v) ? with schmitt trigger added fo r noise-immune pr ogramming input ? 18-bit programmable input fr equency divider (including a 64/65 prescaler) with divide ratio range from 4032 to 262143 ? 13-bit programmable reference frequency divider (including a 8 prescaler) with divide ratio range from 40 to 65528 ? optional lock detector output ( ld, f r /2, f v /2 ) ? charge pump output for passive low-pass filter ? wide tuning range of charge pum p output for external vco ( v ss +0.5 to v dd2 -0.5 ) ? switchover terminal for constant of loop filter or general open drain output ? reference oscillator buffer output ? programmable stand-by control ? tssop 16l package (0.65mm pitch) applications ? pager ? family radio service (frs) ? wireless communication system
advance information FS8308 page 2 april 2003 package and pin assignment: 16l, tssop note: tolerance + 0.1mm unless otherwise specified symbols dimensions in mm dimensions in inch min. nom. max. min. nom. max. a --- --- 1.20 --- --- 0.048 a1 0.05 --- 0.15 0.002 --- 0.006 a2 0.80 1.00 1.05 0.031 0.039 0.041 b 0.19 --- 0.30 0.007 --- 0.012 c 0.09 --- 0.20 0.004 --- 0.008 d 4.90 5.00 5.10 0.193 0.197 0.201 e --- 6.40 --- --- 0.252 --- e1 4.30 4.40 4.50 0.169 0.173 0.177 e --- 0.65 --- --- 0.026 --- l 0.45 0.60 0.75 0.018 0.024 0.030 y --- --- 0.10 --- --- 0.004 0 --- 8 0 --- 8 xin xout vdd2 nc do vss fin vdd1 bo test sw le data clk ld nc 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 himark FS8308
advance information FS8308 page 3 april 2003 pin descriptions block diagram number name i/o description 1xin i reference crystal oscillator or external clock input with internally biased amplifier (any external input to xin must be ac-coupled) 2 xout o reference crystal oscill ator or external clock output 3 vdd2 power nominal 3.0 v supply voltage 4 nc nc no connection 5 do o single-ended charge pump outp ut for passive low-pass filter 6 vss gnd ground 7fin i vco frequency input with internally biased input amplifier (any external input to fin must be ac-coupled) 8 vdd1 power nominal 1.0 v supply voltage 9 nc nc no connection 10 ld o lock detector output (high when pll is locked) 11 clk i shift register clock input 12 data i serial data input 13 le i latch enable input 14 sw o switchover terminal for constant of loop filter or a general open drain output 15 test i test mode control input wi th internal pull-down resistor 16 bo o terminal of reference crys tal oscillator buffer output pfd charge pump fin data clk le test xin control logic n-counter r-counter shift register n-latch r-latch 8 64/65 ld do xout lock detector window generator s-latch sw bo sw
advance information FS8308 page 4 april 2003 absolute maximum ratings v ss = 0 v recommended oper ating conditions v ss = 0 v parameter symbol rating unit supply voltage v dd1 v ss ? 0.3 to v ss + 2.0 v v dd2 v ss ? 0.3 to v ss + 6.0 v input voltage range v fin v ss ? 0.3 to v dd + 0.3 v operating temperature range t ps ?30 to 60 o c storage temperature range t stg ?40 to 125 o c soldering temperature range t sld 255 o c soldering time range t sld 10 s parameter symbol va l u e unit min. typ. max. supply voltage range v dd1 0.95 1.0 2.0 v v dd2 2.4 3.0 3.6 v operating temperature t a ?30 25 60 o c
advance information FS8308 page 5 april 2003 electrical characteristics (v dd1 = 0.95 to 2.0 v, v dd2 = 2.4 to 3.6 v, v ss = 0 v, t a = 0 to 60 c unless otherwise noted) parameter symbol condition va l u e unit min. typ. max. current consumption i dd,total v dd1 = 1.0 v f fin = 500 mhz f xin =24 mhz 1.2 1.5 ma standby current consumption i dd,standby ps=?h? 10 a fin operating frequency range f fin p fin = -15dbm v dd1 = 1.0 v, ps=?l? 20 500 mhz xin operating frequency range f xin v dd1 = 1.0 v 7 40 mhz fin input voltage swing p fin -15 dbm xin input voltage swing v xin 0.3 v pk-pk clk, data, le logic low input voltage v il 0.3 v clk, data, le logic high input voltage v ih v dd - 0.3 v xin logic low input current i il,xin v il = 0 v 10 a xin logic high input current i ih,xin v ih = v dd1 10 a fin logic low input current i il,fin v il = 0 v 60 a fin logic high input current i ih,fin v ih = v dd1 60 a charge pump drive current i do v dd2 = 3.0v, v do = 1.5v 1.0 ma charge pump sink current i do v dd2 = 3.0v, v do = 1.5v 1.0 ma ld, fv, fr logic low output current i ol v ol = 0.4 v 0.1 ma ld, fv, fr logic high output current i oh v oh = v dd2 ? 0.4 v 0.1 ma sw logic low output current i sw,off sw = ?l? v sw = v dd2 = 3.0v 10 a sw logic high output current i sw,on sw = ?h? v sw = v dd2 = 3.0v 2.8 ma data to clk setup time t su1 2 s clk to le setup time t su2 2 s hold time t hold 2 s
advance information FS8308 page 6 april 2003 functional description programmable input frequency divider the vco input to the fin pin is divided by the programmable divider and then internally output to the phase/frequency detector (pfd) as f v . the programmable input frequency divider consists of a 64/65 ( p / p +1) dual-modulus prescaler in prior to a 18-bit ( n ) counter, which is further co mprised of a 6-bit swallow ( a ) counter, and a 12-bit main ( b ) counter. the total divide ratio, n , is related to values for p , a , and b through the relation with the minimum available programma ble divisor for continuous counting is given by and the valid total divide ratio range for the input divider is take n=10000 for example, since p=64 and hen ce that b=156 and a=16. therefore, the binary codes of b and a should be 0000 1001 1100 and 010000, respectively. an alterna- tive approach is to translate th e decimal n into binary code di rectly. and then just take the last 6-bit as a and the remaining 12-bit as b. by fa r the binary code of n= 10000 is 00 0010 0111 0001 0000. one can get the sa me result as the former method. programmable reference frequency divider the crystal oscillator output is divided by the programmable divider and then internally output to the pfd as f r . the programmable refe rence frequency divider consists of a fixed 8 ( s ) prescaler and a 13-bit reference ( r ) counter. the total divide ratio, t , is related to values for s and r through the relation the usable divisior range of the refere nce counter is and therefore, the valid total divide ratio range for the reference divider is (in steps of 8.) np 1 + () ap ba ? () + pba , + == ba . pp 1 ? () 64 63 4032, == m 4032 to 262143. = tsr 8 r . == r 5 to 8191 = t 40 to 65528 =
advance information FS8308 page 7 april 2003 serial input data format the divsors of the input and reference divide rs are input using a 20-bit serial interface consisting of separate clock (clk ), data (data), and latch enab le (le) lines. the format of the serial data is shown in fig. 1. the data on the data line is written to the shift reg- ister on the rising edge of the clk signal and is input with msb first. the last two bits are recognized as the latch select control bits. data on the da ta line should be changed on the falling edge of clk, and le should be held low while data is being written to the shift register. data is transferred from the shift re gister to either one of the frequency divider latches or the optional control la tch when le is set high. when the latch select control bits are set high-low or low-low, data is loaded to the 18-bit n -counter latch, and when the latch select control bits are se t high-high, the 2 msbs are ignored, the next 13 data bits are loaded to the 13-bit r -counter latch and the remaining 3 ls bs are used to control testing modes and should be set as follows for norma l operation: r14 = high, r15 = low, r16 = low. to disable ld output ( i.e. set ld low), r14 s hould be set low. when the latch select control bits are set low-high, the 2 msbs are recognized as ps and sw, which are used as stand-by control and open drain ou tput control, respectively. the detail of two control bits setting is summarized in table 1. in normal work condition, ps is set to low. when ps is programmed to high, it wi ll enter stand-by mode. serial input data timing wave forms are shown in fig. 2. fig. 1 ? serial input data format table 1: control bit setting 1st cb 2nd cb fetching target of serial data input x0 n-counter 0 1 ps and sw 11 r-counter 2nd control bit lsb 18-bit data for n-counter 13-bit data for r-counter r15 r16 r14 ignored ignored sw ps optional control 1st control bit msb
advance information FS8308 page 8 april 2003 fig. 2 ? serial input data timing waveforms t su1 t su2 t hold data clk le data clk le 234567891011121314151617 1 18 19 20 1st cb 2nd cb msb lsb
advance information FS8308 page 9 april 2003 phase/frequency detector (pfd) the pfd compares an internal input frequency divider output signal, f v , with an internal reference frequency di vider output signal, f r , and generates an error signal, do, which is proportional to the phase error between f v and f r . the do output is intended for use with a passive filter as shown in fig. 2. lock detector (ld) when phase comparator detect s phase difference, ld termin al outputs ?l?. when phase comparator locks, ld terminal outputs ?h?. on standby, outputs ?h?. the criteria for lock condition is that the phase difference between f v and f r is less than 2/xin and continues for more than three consecutive times. the input/output waveforms for the pfd and ld are shown in fig. 3. fig. 2 ? passive low-pass filter circuit fig. 3 ? pfd input/output waveforms do to vco r1 c1 c2 high-z high-z high-z f r f v do ld < 2/xin < 2/xin < 2/xin 2/xin
advance information FS8308 page 10 april 2003 stand-by mode the stand-by mode for the pll is entered by programming the ps bit to high. in the stand- by mode, the xin and fin amplifiers, n -counter, and r -counter are stopped, as well as the internal current bias for charge pump block, the n - and r -counters are also reset, and the do and db outputs are set to the high impedance state. as lo ng as voltage is supplied to v dd2 , data loaded to the latches is kept. to exit from stand-by mode to normal operation, the ps bit must be programmed to low. reference crystal oscillator buffer output (bo) this ic provides a reference cr ystal oscillator buffer output in tended to be used as a crys- tal local oscillator to a 2nd mixer. the terminal is represented as bo. for cases to enhance the buffer output swing, increasing v dd1 will be an efficient way. filter switch control (sw) control of sw terminal by ?sw? bit. this te rminal is for switchi ng time-constant of loop filter. output type of this te rminal is open drain output. wh en constant of loop filter doesn?t change by this switch, ge neral open drain output is availa ble. note that there is an internal 200 ? resistor connected between a nd drain terminal and output pin.
advance information FS8308 page 11 april 2003 application circuit bo test sw le data clk ld nc xin xout vdd2 nc do vss fin vdd1 dc/dc converter cpu lcd driver lcd driver rom ram decoder lpf lna 1st mixer 1st if amplifier 2nd mixer 2nd if amplifier discriminator wave shaper frequency multiplier ( 4,5) 2nd lo 1st lo himark FS8308
advance information FS8308 page 12 april 2003 typical characteristics fin input sensitivity vs. input frequency 0 100 200 300 400 500 600 -40 -36 -32 -28 -24 -20 -16 -12 -8 -4 0 vdd2=3.0v f xin =24mhz, r=5 input sensitivity (dbm) f fin (mhz) vdd1=1.0v vdd1=1.1v vdd1=1.2v
advance information FS8308 page 13 april 2003 current consumption of idd1 vs. operating frequency current consumption of idd2 vs. supply voltage vdd2 0 100 200 300 400 500 600 0.0 0.4 0.8 1.2 1.6 2.0 vdd1=1.0v vdd1=1.1v vdd1=1.2v vdd2=3.0v, pfin=-15dbm f xin =24mhz, r=5 idd1 (ma) f fin (mhz) 1.6 2.0 2.4 2.8 3.2 3.6 4.0 0.16 0.20 0.24 0.28 0.32 0.36 0.40 idd2 (ma) vdd2 (v)
advance information FS8308 page 14 april 2003 charge pump output characteristics charge pump output current vs. power supply voltage 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 vdd2=3.0v f r < f v f r > f v i do (ma) v do (v) drive current sink current 1.5 2.0 2.5 3.0 3.5 4.0 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 charge pump output current vdd2 2 1 v do = i do (ma) vdd2 (v) drive current sink current
advance information FS8308 page 15 april 2003 single voltage operation this ic requires two separate power supplies to operate. if only one voltage source is available, ex. use battery to serve as power s ource, the user can apply the configuration as shown in the following which is refe rred to as single voltage operation. since there is only one voltage source provided in the so-c alled single voltage configura- tion, which is directly connected to v dd2 , one needs to choose a reasonable r value to set v dd1 to operate within the safe region, whose requirement is v dd1 > 0.95v. keep in mind that the lower v dd1 is, the less current this ic will consume, but the poorer crystal buffer output it drives. in order to balance the tr ade-off between the current consumption and crystal buffer driving capability, v dd1 is suggested to be about 1.1v. v dd1 vs. v dd2 for vari- ous r at fin=470mhz is plotted in the following figure. no te that although smaller resistor r makes this ic consume more current, th e reward is with wi der power supply input range. typical value of r is recommended to be around 1.6k ?. . single voltage characteristic: vdd1 vs. vdd2 for various r vdd2 vdd1 himark FS8308 r power supply 1.5 2.0 2.5 3.0 3.5 4.0 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 safe operation region fin=470mhz, pfin=-10dbm xin=24mhz, n=4032, r=5 vdd1 (v) vdd2 (v) r=1.2k r=1.6k r=1.8k r=2.0k

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